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3 bit parallel to serial converter9/21/2023 ![]() ![]() ![]() Bit-serial multipliers can be designed as systolic arrays: synchronous arrays of processing element that are interconnected by only short, local wires thus allowing very high clock rates. Furthermore, in applications that call for a large number of independent multiplications, multiple bit-serial multiplier may be more cost- effective than a complex highly pipelined unit. In such a case, using a parallel multiplier would be quite wasteful, since the parallelism may not lead to any speed benefit. In addition, in certain application contexts inputs are supplied bit-serially anyway. In fact,the compactness of the design may allow us to run a bit- serial multiplier at a clock rate high enough to make the unit almost competitive with much more complex designs with regard to speed. ![]()
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